Download Presentation PowerPoint Slideshow about 'HDMI-enabled Designs Using the ADV7513' - cher An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. Interpreter CECCLK CEC Audio Data Capture S/PDIF MCLK 4:2:2 ↕ 4:4:4 & Color Space Converter HDCP Keys* I2S[3:0] LRCLK SCLK HDCP Encryption Video Data Capture D[23:0] TMDS Outputs HS Tx0 VS DE Tx1 Registers & Config. Logic CLK Tx2 HPD TxC INT I2C Slave I2C Master SDA SCL HDCP & EDID Micro- controller DDCSDA DDCSCL • Supports display resolutions at 25~165 MHz (up to 1080p/UXGA) • Incorporates extended HDMI v1.3/1.4 features • Supports extended colorimetry (e.g. X.v.ColorTM) • HBR audio formats • DST/DSD audio formats • 3D Ready (720p50/60 & 1080p24/25/30) • Integrated CEC support • Buffer CEC signals • Off-loads real-time monitoring from host µP • Low standby power • Software driver Easy implementation • On-chip HDCP support • Automated or programmable color space converter • Flexible video inputs: • RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2 • 24-bit input interface • Supports ITU656 style embedded syncs • Integrated I2C Master for DDC bus • +5V tolerant I/Os for HPD and I2C • 1.8V & 3.3V supplies. • I2C slave Interface • Standard I2C protocol up to 400KHz • Hardware considerations • SDA and SCL pins should be connected to an I2C Master • 2KΩ (+/-5%) pull-up resistors to 1.8V or 3.3V recommended for each signal • Software considerations • Contains four memory maps • “Main” register device address is 0x72 (where the R/W~ bit is the LSB) • Contains all non-CEC status and control registers • “Packet Memory” device address is set by register 0x45 of the Main map. • Default setting is 0x70 • “EDID Memory” device address is set by 0x43 of the Main map • Default setting is 0x7E • Used to store EDID that is automatically retrieved from HDMI sink device • “CEC Memory” device address is set by 0xE1 of the Main map • Default setting is 0x78 • Used for CEC related control and command storage See schematic. • Interrupts (continued) • Interrupt handling • The figure below shows the process of detecting and clearing an interrupt • The interrupt pin and interrupt register become active simultaneously when an event triggers an interrupt • System software processes the interrupt, and then writes a ‘1’ to the interrupt register to clear the register and set the interrupt pin back to inactive • The pin will remain active until each active interrupt register is cleared • Interrupt handling example in Programming Guide Wait for Interrupt (INT pin inactive, Int. Registers = 0) Write ‘1’ to interrupt register Event causes an interrupt Process Interrupt (INT pin active, Int. Register = 1). • Hot-plug Detect (HPD) • Detects if a DVI or HDMI sink is connected • Voltage on HPD > 1.2V = sink is connected • Hardware considerations • HPD connects directly to HDMI connector • 10KΩ pull down resistor to ground recommended • ESD device may also be connected • Software considerations • Use HPD interrupt or status (R0x42[6]) to initiate ADV7513 configuration • Start with powering up the device via R0x41[6] • “Quick-Start Guide” section provided in the Programming Guide • When HPD is low, some registers will be reset to their default values and cannot be written to: See schematic. • Software Considerations • “Input ID” register (0x15[3:1]) should be set to reflect the video data format, color space, bus width, # bits per color, and sync type that is input to the ADV7513 from the system SoC • “4:2:2 Width” register (0x16[5:4]) sets the bits-per-color when using an Input ID of 3, 4, or 6 • “Input Style” register (0x16[3:2]) sets the pin mapping for video input data • 01 = style 2, 10 = style 1, 11 = style 3 • See Programming Guide or Hardware User’s Guide for pin mapping details. Baxter tempcon oven manual. • Supports I2S, and SPDIF audio from 32KHz up to 192KHz and HBR at 768KHz • I2S formats • Standard • left-justified • right-justified • direct AES3 stream • SPDIF formats • 2-channel LPCM • IEC61937 encoded multi-channel audio • HBR • I2S Style • BPM Style • Hardware Considerations • I2S requires SCLK and LRCLK input (MCLK optional via Hsync pin) • SPDIF does not require a separate sampling clock (MCLK optional) • Match trace length of audio signals to optimize audio data capture • Add series termination resistors close to the audio source to minimize impedance mismatch. • “Output Format” register bit (0x16[7]) selects 4:2:2 or 4:4:4 • Output color space is determined by the state of the Color Space Converter (CSC) • The Y1Y0 bits of the AVI Infoframe (0x55[6:5]) should be set to match the HDMI output format • More information on the CSC on slide 30 • HDMI uses 4 TMDS pairs • 3 data pairs at up to 1.65GB • Clock pair up to 165MHz • Each pair should be routed differentially with 100Ω impedance (50Ω each to ground) • Low capacitance (. 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